The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for measuring data switching activity in a microprocessor.
There is an emerging customer requirement for better power and thermal management in computing systems. Customers increasingly expect systems to behave in such a way as to be power-efficient. Customers also want the ability to set policies that trade off power and performance in order to meet their particular objectives. For example, customers want to be able to over-provision their installations but be able to take advantage of the variability in workloads and utilization to ensure that the systems operate correctly and within the limits of the available power and cooling.
Today's microprocessors deploy several sophisticated power management schemes. These power management schemes require on-the-fly power measurements. However, power measurement of a microprocessor on-the-fly is a difficult task. Power measurement is even more difficult at the sub-unit level of a microprocessor, such as at a core level, L2 cache level, or the like. While power proxy architectures use sets of counters to approximate power consumed in a core, L2, L3, or the like, to aid power management decisions, power proxy architectures lack accuracy due to the fact the data switching power is not taken into account.